Fuse array structure

ABSTRACT

The present disclosure provides a semiconductor structure with a fuse array structure having a buried word line disposed within a substrate. The semiconductor structure includes a substrate having a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a first gate structure disposed over the first doped region and electrically connected to a first bit line; a second gate structure to disposed over the first surface of the substrate and electrically connected to a second bit line; and a buried word line disposed within the first recess and disposed between the first gate structure and the second gate structure. The second gate structure is at least partially disposed within the second recess of the substrate.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the priority benefit of U.S. provisionalapplication Ser. No. 62/785,359 filed on Dec. 27, 2018. The entirety ofthe above-mentioned patent application is hereby incorporated byreference herein and made a part of this specification.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. Non-ProvisionalApplication No. 16/677,104 filed on Oct. 29, 2019. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

TECHNICAL FIELD

The present disclosure relates to a semiconductor structure, andparticularly relates to a fuse array structure having a buried word linedisposed within a substrate.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are essential for many modern applications. Amongthe semiconductor devices, memory devices such as dynamic random accessmemory (DRAM) have assumed an important role. The memory device includesseveral memory cells arranged in rows and columns over a substrate, andinformation of each memory cell is accessible by bit lines and wordlines extending over a surface of the substrate.

With the advancement of electronic technology, capacity of a fuse arraystructure continues to increase. In other words, a density of the fusearray structure arranged over the substrate is increased. Accordingly,it is difficult to maintain sufficient isolation between electricalcomponents in the fuse array structure.

Therefore, there is a continuous need to improve a structuralconfiguration of the semiconductor device.

This Discussion of the Background section is provided for backgroundinformation only. The statements in this Discussion of the Backgroundare not an admission that the subject matter disclosed in thisDiscussion of the Background section constitutes prior art to thepresent disclosure, and no part of this Discussion of the Backgroundsection may be used as an admission that any part of this application,including this Discussion of the Background section, constitutes priorart to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor structurecomprising a substrate including a first surface, a first doped regiondisposed under the first surface, a second doped region disposed underthe first surface, and a recess indented into the substrate and disposedbetween the first doped region and the second doped region; a controlgate structure disposed over the first doped region and electricallyconnected to a control bit line; a fuse gate structure disposed over thesecond doped region and electrically connected to a fuse bit line; and aburied word line disposed between the control gate structure and thefuse gate structure, wherein the buried word line is disposed within therecess of the substrate.

In some embodiments, the buried word line is disposed under and awayfrom the first surface of the substrate.

In some embodiments, the buried word line is disposed under and awayfrom the first doped region and the second doped region.

In some embodiments, the recess extends from the first surface of thesubstrate towards a second surface of the substrate opposite to thefirst surface.

In some embodiments, the fuse gate structure includes a fuse dialetricdisposed on the second doped region.

In some embodiments, the fuse dielectric is breakable when a voltagebias between the buried word line and the fuse bit line is substantiallygreater than 5V.

In some embodiments, the buried word line is disposed under and awayfrom the fuse electric.

In some embodiments, the fuse dielectric includes oxide or metalcontained oxide.

In some embodiments, the first doped region and the second doped regionare of a same conductive type.

In some embodiments, the buried word line includes a conductor and anisolation layer disposed within the recess and between the substrate andthe conductor.

In some embodiments, the isolation layer is disposed conformal to asidewall of the recess.

In some embodiments, the isolation layer includes a first portiondisposed between the conductor and the substrate, and a second portiondisposed under the conductor, and wherein a thickness of the firstportion is substantially greater than a thickness of the second portion.

In some embodiments, the isolation layer includes high-k (high dialetricconstant) dialectric material.

In some embodiments, the control bit line and the fuse bit line aresubstantially orthogonal to the buried word line.

In some embodiments, the control bit line and the fuse bit line aresubstantially parallel to each other.

Another aspect of the present disclosure provides a semiconductorstructure comprising a substrate including a first surface, a firstdoped region disposed under the first surface, a second doped regiondisposed under the first surface, a first recess indented into thesubstrate and disposed between the first doped region and the seconddoped region, and a second recess indented into the substrate andadjacent to the second doped region; a first gate structure disposedover the first doped region and electrically connected to a first bitline; a second gate structure disposed over the first surface of thesubstrate and electrically connected to a second bit line; and a buriedword line disposed within the first recess and disposed between thefirst gate structure and the second gate structure, wherein the secondgate structure is at least partially disposed within the second recessof the substrate.

In some embodiments, a depth of the second recess is substantially lessthan a depth of the first recess.

In some embodiments, the second gate structure includes a gatedialectric disposed within the second recess of the substrate.

In some embodiments, the gate dielectric is breakable upon a voltagebias between the buried word line and the second bit line.

In some embodiments, the voltage bias between the buried word line andthe second bit line is substantially greater than 2V.

The foregoing has outlined rather broadly the features and technicaladvantages of the present disclosure in order that the detaileddescription of the disclosure that follows may be better understood.Additional features and advantages of the disclosure will be describedhereinafter, and form the subject of the claims of the disclosure. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiment disclosed may be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe same purposes of the present disclosure. It should also be realizedby those skilled in the art that such equivalent constructions do notdepart from the spirit and scope of the disclosure as set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure may be derivedby referring to the detailed description and claims when considered inconnection with the Figures, where like reference numbers refer tosimilar elements throughout the Figures.

FIG. 1 is a schematic top view of a first semiconductor structure inaccordance with some embodiments of the present disclosure.

FIG. 2 is a schematic cross-sectional view of the first semiconductorstructure along a line A-A′ of FIG. 1 in accordance with someembodiments of the present disclosure.

FIG. 3 is a schematic top view of a second semiconductor structure inaccordance with some embodiments of the present disclosure.

FIG. 4 is a schematic cross-sectional view of the second semiconductorstructure along a line B-B′ of FIG. 3 in accordance with someembodiments of the present disclosure.

FIG. 5 is a schematic top view of a third semiconductor structure inaccordance with some embodiments of the present disclosure.

FIG. 6 is a schematic cross-sectional view of the third semiconductorstructure along a line C-C′ of FIG. 5 in accordance with someembodiments of the present disclosure.

DETAILED DESCRIPTION

The following description of the disclosure accompanies drawings, whichare incorporated in and constitute a part of this specification, andillustrate embodiments of the disclosure, but the disclosure is notlimited to the embodiments. In addition, the following embodiments canbe properly integrated to complete another embodiment.

References to “one embodiment,” “an embodiment,” “exemplary embodiment,”“other embodiments,” “another embodiment,” etc. indicate that theembodiment(s) of the disclosure so described may include a particularfeature, structure, or characteristic, but not every embodimentnecessarily includes the particular feature, structure, orcharacteristic. Further, repeated use of the phrase “in the embodiment”does not necessarily refer to the same embodiment, although it may.

As used herein, the term “anti-fuse” refers to a semiconductor devicewhich is a normally open circuit. The anti-fuse can be “blown” to becomea short circuit when a programming voltage is applied. In someembodiments of the present disclosure, the anti-fuse structure includesin a gate oxide (GOX) anti-fuse structure.

In order to make the present disclosure completely comprehensible,detailed steps and structures are provided in the following description.Obviously, implementation of the present disclosure does not limitspecial details known by persons skilled in the art. In addition, knownstructures and steps are not described in detail, so as not tounnecessarily limit the present disclosure. Preferred embodiments of thepresent disclosure will be described below in detail. However, inaddition to the detailed description, the present disclosure may also bewidely implemented in other embodiments. The scope of the presentdisclosure is not limited to the detailed description, and is defined bythe claims.

In a fuse array structure, an antifuse dielectric such as a very thinoxide barrier layer is employed between a pair of conductors. Formationof a conductive channel between the conductors across the antifusedielectric is performed by a dielectric breakdown of the antifusedielectric. The antifuse dielectric can be broken down by applying ahigh voltage pulse across the antifuse dielectric.

With the technological advancement, functionality and capacity of thefuse array structure is increased. However, an overall size of the fusearray structure continues to become smaller and smaller. As such, anisolation distance between the antifuse dielectric and the word line orbit line may not be sufficient for such a high voltage pulse of thedielectric breakdown. As a result, reliability of the fuse arraystructure is adversely affected.

In the present disclosure, a semiconductor structure is disclosed. Thesemiconductor structure includes a substrate including a first surface,a first doped region disposed under the first surface, a second dopedregion disposed under the first surface, and a recess indented into thesubstrate and disposed between the first doped region and the seconddoped region; a control gate structure disposed over the first dopedregion and electrically connected to a control bit line; a fuse gatestructure disposed over the second doped region and electricallyconnected to a fuse bit line; and a buried word line disposed betweenthe control gate structure and the fuse gate structure, wherein theburied word line is disposed within the recess of the substrate. Sincethe buried word line is buried in the substrate, a distance between thethe buried word line and the fuse gate structure can be maximized.Therefore, electrical isolation between the buried word line and thefuse gate structure is improved.

FIG. 1 is a schematic top view of a first semiconductor structure 100 inaccordance with some embodiments of the present disclosure. FIG. 2 is aschematic cross-sectional view of the first semiconductor structure 100along a line A-A′ of FIG. 1.

In some embodiments, the first semiconductor structure 100 is formedadjacent to a memory device such as a dynamic random access memory(DRAM) device or the like. In some embodiments, the first semiconductorstructure 100 is a fuse array structure or a part of the fuse arraystructure.

In some embodiments, the first semiconductor structure 100 includesseveral conductive lines extending over a substrate 101. In someembodiments, the conductive lines are arranged in rows and columns. Insome embodiments, the conductive lines include several bit lines (102,103) and several word lines 104. In some embodiments, the bit lines(102, 103) are substantially orthogonal to the word lines 104. In someembodiments, the bit lines (102, 103) are electrically isolated fromeach other. In some embodiments, the word lines 104 are electricallyisolated from each other.

In some embodiments, the bit lines include a control bit line 102 and afuse bit line 103. In some embodiments, information or data can bestored in the memory through the bit line when the gate is opened by theword line. In some embodiments, the control bit line 102 and the fusebit line 103 are substantially parallel to each other.

In some embodiments, the first semiconductor structure 100 includes thesubstrate 101. In some embodiments, the substrate 101 is asemiconductive substrate. In some embodiments, the substrate 101includes semiconductive material such as silicon, germanium, gallium,arsenic, or combinations thereof. In some embodiments, the substrate 101is a silicon substrate. In some embodiments, the substrate 101 includesmaterial such as ceramic, glass or the like. In some embodiments, thesubstrate 101 is a silicon on insulator (SOI) substrate, wherein aninsulation layer is disposed over a silicon substrate. In someembodiments, the substrate 101 is fabricated with a predeterminedfunctional circuit thereon.

In some embodiments, the substrate 101 includes a first surface 101 aand a second surface 101 b opposite to the first surface dopants. Insome embodiments, an active region 101 c (shown in FIG. 1) is disposedover or in the substrate 101. In some embodiments, the active region 101c is disposed over or proximal to the first surface 101 a of thesubstrate 101. In some embodiments, the active region 101 c is disposeddiagonally over the first surface 101 a of the substrate 101.

In some embodiments, the active region 101 c includes several dopedregions (101 d, 101 e) (shown in FIG. 2). In some embodiments, each ofthe doped regions (101 d, 101 e) includes the same type of dopants. Insome embodiments, each of the doped regions (101 d, 101 e) includes atype of dopant that is different from the type of dopant included in theother doped region (101 d, 101 e). In some embodiments, the dopedregions (101 d, 101 e) include a first doped region 101 d and a seconddoped region 101 e. In some embodiments, the first doped region 101 dand the second doped region 101 e are disposed over or under the firstsurface 101 a of the substrate 101. In some embodiments, the first dopedregion 101 d and the second doped region 101 e include dopants of thesame type. In some embodiments, the first doped region 101 d and thesecond doped region 101 e include N type dopants. In some embodiments,the first doped region 101 d and the second doped region 101 e are ofthe same conductive type.

In some embodiments, the substrate 101 includes a recess 101 f indentedinto the substrate 101 and disposed between the first doped region 101 dand the second doped region 101 e. In some embodiments, the recess 101 fis indented into the substrate 101 from the first surface 101 a towardsthe second surface 101 b of the substrate 101. In some embodiments, therecess 101 f is disposed under the active region 101 c of the substrate101. In some embodiments, the recess 101 f is disposed under the firstdoped region 101 d and the second doped region 101 e.

In some embodiments, the first semiconductor structure 100 includes acontrol gate structure 105 disposed over the first doped region 101 dand electrically connected to the control bit line 102. In someembodiments, the control gate structure 105 includes a masking layer 105a, a metallic layer 105 b and a polysilicon layer 105 c. In someembodiments, the metallic layer 105 b is disposed over the polysiliconlayer 105 c, and the masking layer 105 a is disposed over the metalliclayer 105 b. In some embodiments, the masking layer 105 a includessilicon nitride, nitride or the like. In some embodiments, metalliclayer 105 b includes tungsten, titanium element or the like.

In some embodiments, the first semiconductor structure 100 includes afuse gate structure 106 disposed over the second doped region 101 e andelectrically connected to the fuse bit line 103. In some embodiments,the fuse gate structure 106 includes a fuse dielectric 106 a, a maskinglayer 106 b, a metallic layer 106 c and a polysilicon layer 106 d. Insome embodiments, the fuse dielectric 106 a is under the masking layer106 b, the metallic layer 106 c and the polysilicon layer 106 d. In someembodiments, the masking layer 106 b includes silicon nitride, nitrideor the like. In some embodiments, metallic layer 106 c includestungsten, titanium element or the like. In some embodiments, the fusedielectric 106 a includes oxide, or metal contained oxide or the like.

In some embodiments, the first semiconductor structure 100 includes aburied word line 104 disposed within the substrate 101. In someembodiments, the buried word line 104 is disposed between the controlgate structure 105 and the fuse gate structure 106. In some embodiments,the buried word line 104 is disposed within the recess 101 f of thesubstrate 101. In some embodiments, the buried word line 104 is disposedunder and away from the first surface 101 a of the substrate 101. Insome embodiments, the buried word line 104 extends between the firstsurface 101 a and the second surface 101 b of the substrate 101. In someembodiments, the buried word line 104 is disposed under and away fromthe first doped region 101 d and the second doped region 101 e.

In some embodiments, the buried word line 104 is configured to control adielectric breakdown of the fuse dielectric 106 a. In some embodiments,the buried word line 104 includes a conductor 104 a within the recess101 f. In some embodiments, the conductor 104 a includes tungsten,titanium nitride, tungsten nitride, tantalum nitride, and thecombination there of, etc.

In some embodiments, the buried word line 104 is surrounded by anisolation layer 104 b. In some embodiments, the isolation layer 104 b isdisposed within the recess 101 f of the substrate 101 and between thesubstrate 101 and the conductor 104 a. In some embodiments, theisolation layer 104 b includes a first portion 104 b-1 and a secondportion 104 b-2. In some embodiments, the first portion 104 b-1 isdisposed between the conductor 104 a and the substrate 101. In someembodiments, the second portion 104 b-2 is disposed under the conductor104 a. In some embodiments, the second portion 104 b-2 surround an endportion of the conductor 104 a. In some embodiments, a thickness of thefirst portion 104 b-1 is substantially greater than a thickness of thesecond portion 104 b-2. In some embodiments, the isolation layer 104 bincludes high-k (high dielectric constant) dielectric material such ashafnium oxide (HfO2).

In some embodiments, a conductive path across the fuse dielectric 106 ais absent if no breakdown voltage is applied between the buried wordline 104 and the first fuse gate structure 106. In other words, aconductive path across the fuse dielectric 106 a is formed when thebreakdown voltage is applied between the buried word line 104 and thefirst fuse gate structure 106. In some embodiments, the fuse dielectric106 a undergoes a dielectric breakdown process when the breakdownvoltage is applied between the buried word line 104 and the first fusegate structure 106. In some embodiments, the fuse dielectric 106 a isbreakable when a voltage bias between the buried word line 104 and thefuse bit line 103 is substantially greater than 5V. In some embodiments,the voltage bias is about 5V to about 6V. In some embodiments, thevoltage bias is about 6V to about 10V. In some embodiments, the fusedielectric 106 a is damaged upon the dielectric breakdown process.

FIG. 3 is a schematic top view of a second semiconductor structure 200in accordance with some embodiments of the present disclosure. FIG. 4 isa schematic cross-sectional view of the second semiconductor structure200 along a line B-B′ of FIG. 3. In some embodiments, the secondsemiconductor structure 200 includes a substrate 201, which is in aconfiguration similar to the substrate 201 described above orillustrated in FIG. 2.

In some embodiments, the substrate 201 includes a first surface 201 a(shown in FIG. 4), a second surface 201 b opposite to the first surface201, a first doped region 201 d and a second doped region 201 e, whichare in configurations similar to those described above or illustrated inFIG. 2. In some embodiments, the substrate 201 includes a first recess201 f and a buried word line 204 within the first recess 201 f, whichare in configurations similar to those described above or illustrated inFIG. 2.

In some embodiments, the substrate 201 includes a second recess 201 gindented into the substrate 201 and adjacent to the second doped region201 e. In some embodiments, the second recess 201 g extends from thefirst surface 201 a towards the second surface 201 b of the substrate201. In some embodiments, the first recess 201 f and the second recess201 g are formed separately or simultaneously. In some embodiments, adepth of the second recess 201 g is substantially less than a depth ofthe first recess 201 f.

In some embodiments, the second semiconductor structure 200 includes acontrol gate structure 205 disposed over the first doped region 201 dand electrically connected to a control bit line 202. In someembodiments, the control gate structure 205 and the control bit line 202are in configurations similar to those described above or illustrated inFIG. 2.

In some embodiments, the second semiconductor structure 200 includes afuse gate structure 210 disposed over the first surface 210 a of thesubstrate 201 and electrically connected to a fuse bit line 203. In someembodiments, the fuse gate structure 210 includes a masking layer 210 a,a metallic layer 210 b under the masking layer 210 a, and a spacer 210 cadjacent to or surrounding the masking layer 210 a and the metalliclayer 210 b.

In some embodiments, the masking layer 210 a includes silicon nitride,nitride or the like. In some embodiments, the metallic layer 210 bincludes polycrystalline silicon, titanium nitride, tungsten, or thelike. In some embodiments, the second fuse gate structure 210 iselectrically connected to the fuse bit line 203 through a contact abovethe masking layer 210 a. In some embodiments, the fuse dielectric 210 dincludes oxide, silicon dioxide, etc. In some embodiments, the spacer210 c includes nitride, silicon nitride, oxide, etc.

In some embodiments, the metallic layer 210 b is at least partiallydisposed within the second recess 210 g of the substrate 201. In someembodiments, the metallic layer 210 b is disposed on the fuse dielectric210 d. In some embodiments, at least a portion of the metallic layer 210b is disposed under the first surface 201 a of the substrate 201. Insome embodiments, the fuse dielectric 210 d is disposed within thesecond recess 210 g. In some embodiments, the fuse dielectric 210 d isdisposed between the metallic layer 210 b and the substrate 201. In someembodiments, the fuse dielectric 210 d is conformal to a sidewall of thesecond recess 201 g.

In some embodiments, the buried word line 204 is disposed under and awayfrom the fuse dialectric 210 d. In some embodiments, a conductive pathacross the fuse dielectric 210 d is absent if no breakdown voltage isapplied between the second fuse gate structure 210 and the buried wordline 204. In other words, a conductive path across the fuse dielectric210 d is formed when a breakdown voltage is applied between the secondfuse gate structure 210 and the buried word line 204.

In some embodiments, the fuse dielectric 210 d undergoes a dielectricbreakdown process when the voltage is applied between the second fusegate structure 210 and the buried word line 204. In some embodiments,the fuse dielectric 210 d is breakable when a voltage bias between theburied word line 204 and the fuse bit line 203 is substantially greaterthan 2V. In some embodiments, the voltage bias is about 2V to about 4V.In some embodiments, the voltage bias is about 5V to about 10V. In someembodiments, the fuse dielectric 210 d is damaged upon the dielectricbreakdown process.

FIG. 5 is a schematic top view of a third semiconductor structure 300 inaccordance with some embodiments of the present disclosure. FIG. 6 is aschematic cross-sectional view of the third semiconductor structure 300along a line C-C′ of FIG. 5. In some embodiments, the thirdsemiconductor structure 300 includes a substrate 301, which is in aconfiguration similar to the substrate 101, 201 described above orillustrated in FIG. 2 or FIG. 4.

In some embodiments, the substrate 301 includes a first surface 301 a, asecond surface 301 b opposite to the first surface 301, a first dopedregion 301 d, a second doped region 301 e, a first recess 301 f and asecond recess 301 g, which are in configurations similar to thosedescribed above or illustrated in FIG. 4.

In some embodiments, the third semiconductor structure 300 includes agate structure 311 disposed over the first doped region 301 d andelectrically connected to an electrical ground. In some embodiments, thegate structure 311 is electrically connected to a grounded bit line 312.In some embodiments, the gate structure 311 includes a masking layer 311a, a metallic layer 311 b and a polysilicon layer 311 c. In someembodiments, the masking layer 311 a is disposed over the metallic layer311 b, and the metallic layer 311 b is disposed over the polysiliconlayer 311 c. In some embodiments, the masking layer 311 a includessilicon nitride, nitride or the like. In some embodiments, the metalliclayer 311 b includes tungsten, titanium or the like.

In some embodiments, the third semiconductor structure 300 includes afuse gate structure 313 disposed over the first surface 301 a of thesubstrate 301 and electrically connected to a control bit line 302. Insome embodiments, the fuse gate structure 313 includes a masking layer313 a, a metallic layer 313 b under the masking layer 313 a, and aspacer 313 c surrounding the masking layer 313 a and the metallic layer313 b, which are in configurations similar to the fuse gate structure210 described above or illustrated in FIG. 4.

In some embodiments, the metallic layer 313 b is at least partiallydisposed within the second recess 301 g. In some embodiments, the thirdsemiconductor structure 300 includes a fuse dielectric 313 d disposedwithin the second recess 301 g of the substrate 301. In someembodiments, the fuse dielectric 313 d is disposed under the firstsurface 301 a of the substrate 301. In some embodiments, the fusedialetric 313 d is in a configuration similar to the fuse dielectric 210d described above or illustrated in FIG. 4.

In some embodiments, the third semiconductor structure 300 includes aburied word line 304 disposed between the gate structure 311 and thefuse gate structure 313. In some embodiments, the buried word line 304is disposed within the first recess 301 f of the substrate 301. In someembodiments, the buried word line 304 is in a configuration similar tothe buried word line 304 described above or illustrated in FIG. 4.

In some embodiments, the fuse dielectric 313 d undergoes a dielectricbreakdown process when a voltage is applied between the fuse gatestructure 313 and the buried word line 304. In some embodiments, thefuse dialectric 313 d is breakable when a voltage bias between theburied word line 304 and the control bit line 302 is substantiallygreater than 2V. In some embodiments, the voltage bias is about 2V toabout 4V. In some embodiments, the voltage bias is about 5V to about10V.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure as defined by the appended claims. For example,many of the processes discussed above can be implemented throughdifferent methods, replaced by other processes, or a combinationthereof.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present disclosure, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein, may be utilized according tothe present disclosure. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, and steps.

What is claimed is:
 1. A semiconductor structure, comprising: asubstrate including a first surface, a first doped region disposed underthe first surface, a second doped region disposed under the firstsurface, a first recess indented into the substrate and disposed betweenthe first doped region and the second doped region, and a second recessindented into the substrate and adjacent to the second doped region; afirst gate structure disposed over the first doped region andelectrically connected to a first bit line; a second gate structuredisposed over the first surface of the substrate and electricallyconnected to a second bit line; and a buried word line disposed withinthe first recess and disposed between the first gate structure and thesecond gate structure, wherein the second gate structure is at leastpartially disposed within the second recess of the substrate.
 2. Thesemiconductor structure of claim 1, wherein a depth of the second recessis substantially less than a depth of the first recess.
 3. Thesemiconductor structure of claim 1, wherein the second gate structureincludes a gate dielectric disposed within the second recess of thesubstrate.
 4. The semiconductor structure of claim 3, wherein the gatedielectric is breakable upon a voltage bias between the buried word lineand the second bit line.
 5. The semiconductor structure of claim 4,wherein the voltage bias between the buried word line and the second bitline is substantially greater than 2V.
 6. The semiconductor structure ofclaim 1, wherein the buried word line is disposed under and away fromthe first surface of the substrate.
 7. The semiconductor structure ofclaim 1, wherein the buried word line is disposed under and away fromthe first doped region and the second doped region.
 8. The semiconductorstructure of claim 1, wherein the recess extends from the first surfaceof substrate towards a second surface of the substrate opposite to thefirst surface.
 9. The semiconductor structure of claim 1, wherein thesecond gate structure includes a fuse dielectric disposed on the seconddoped region.
 10. The semiconductor structure of claim 9, wherein thefuse dielectric is breakable when a voltage bias between the buried wordline and the fuse bit line is substantially greater than 5V.
 11. Thesemiconductor structure of claim 9, wherein the buried word line isdisposed under and away from the fuse dielectric.
 12. The semiconductorstructure of claim 9, wherein the fuse dielectric includes oxide ormetal contained oxide
 13. The semiconductor structure of claim 1,wherein the first doped region and the second doped region are of a sameconductive type.
 14. The semiconductor structure of claim 1, wherein theburied word line includes a conductor and an isolation layer disposedwithin the recess and between the substrate and the conductor.
 15. Thesemiconductor structure of claim 14, wherein the isolation layer isdisposed conformal to a sidewall of the recess.
 16. The semiconductorstructure of claim 14, wherein the isolation layer includes a firstportion disposed between the conductor and the substrate, and a secondportion disposed under the conductor, and wherein a thickness of thefirst portion is substantially greater than a thickness of the secondportion.
 14. The semiconductor structure of claim 14, wherein theisolation layer includes high-k (high dielectric constant) dielectricmaterial.
 18. The semiconductor structure of claim 1, wherein thecontrol bit line and the fuse bit line are substantially orthogonal tothe buried word line.
 19. The semiconductor structure of claim 1,wherein the control bit line and the fuse bit line are substantiallyparallel to each other.